The present invention relates to binary counters that provide a count signal indicating the number of clock signals that have been received, and more particularly to a method and circuit in which the count signal from a binary counter may be selectively scaled by a factor 2.sup.M so that the count signal indicates that 2.sup.M clock signals have been received for each single clock signal that has been received.
Binary counters find application in digital communication systems where a count of the number of clock signals received is used for various purposes by the system. Binary counters are well known and need not be discussed in detail for an understanding of the present invention. A binary counter provides an (unscaled) count signal indicating the number of clock signals received at the counter, and typically includes N serially connected stages, each for providing an output indicating its state has been changed. The clock signal may be provided synchronously, to all stages simultaneously so that counter output is always correct, or asynchronously, to the first stage so that the signal cascades through the stages and the counter output is only correct when the signal has cascaded to the last stage. Outputs from each stage are provided to a decoder array that provides a count signal. The decoder array may include AND or NAND gates where TRUE equals logic 1, or include OR or NOR gates where TRUE equals logic 0.
The count signal provided by a binary counter indicates the number of clock signals that have been received; each clock signal incrementing the count by one, and thus operating at the speed (frequency) of arrival of the clock signals. In some applications, it is desirable to have a binary counter selectively provide a count that is related to, but not the same as, the number of clock signals received. By way of example, a system may operate normally with a binary counter incrementing its count upon receipt of each clock signal. However, a test or special operating mode of the system may be at different speed (e.g., four times operational speed) so that the binary counter is to provide a count signal that indicates the count is higher than it actually is (four times higher in this example). Prior art systems have been adapted to operate at different speeds by providing a second clock for providing clock signals at the higher rate, or by adapting the decoder array with appropriate control signals and logic. As will be appreciated, these solutions may not be reasonable in all systems, may increase the number of discrete components (and real estate used) for integrated circuits, and may affect normal operation by adding circuitry used in the unscaled mode.
Accordingly, it is an object of the present invention to provide a novel method and device that obviates the problems of the prior art.
It is another object of the present invention to provide a novel method and device in which a scaled count is provided without using a second clock and without modifying the decoder array.
It is yet another object of the present invention to provide a novel method and device in which a scaled count is provided by adapting the N-stages of the counter so that the outputs from the stages indicate the scaled count.
It is still another object of the present invention to provide a novel method and device for providing a scaled count signal in which the first M stages of the N-stage counter are by-passed.
It is a further object of the present invention to provide a novel method and device for providing a scaled count signal in which both the Q and #Q outputs of the first M stages of the N-stage counter are set to true so that the M+1 stage indicates the 2.sup.M clock signals have been received when only one has been received (#Q herein and QN in FIG. 2 indicating "Q not").
It is yet a further object of the present invention to provide a novel method and device for providing a count signal scaled by a factor of 2.sup.M from an N-stage binary counter, where M is an integer less than N, in which Q and #Q outputs from M first stages of the counter are held so that they do not affect counter output, and in which a count signal from the counter indicates that the count is 2.sup.M times the number of input clock signals received.